1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method of producing a semiconductor device comprising a Schottky barrier diode (SBD).
2. Description of the Related Art
An increase in the number of elements per semiconductor chip and miniaturization of semiconductor devices are now required, and thus it is necessary to reduce the areas (dimensions) of an SBD and an electrode of a semiconductor device.
In a conventional process of producing a semiconductor device shown in, e.g., FIG. 1, a metal electrode for forming an SBD and extending to a transistor is made of aluminum or an alloy thereof (Al-Si, Al-Cu, Al-Si-Cu or the like), indicated as "Al" hereinafter. In this case, the semiconductor device is produced in the following manner.
As shown in FIG. 1, a silicon semiconductor substrate 1 comprises a P-type silicon wafer 2, an N.sup.+ -type buried layer 3, and an N-type epitaxial silicon layer 4. The silicon wafer 2 usually has a &lt;111&gt; orientation, and the silicon substrate 1 is selectively and thermally oxidized to form a SiO.sub.2 insulating layer 5 thereon. Regions of the substrate 1 corresponding to the SBD and doped regions of a bipolar transistor are not oxidized, and a trench isolation region 6 reaching the silicon wafer 1 is formed in a conventional process. The trench isolation region 6 comprises a SiO.sub.2 insulating layer 7 coating a trench wall, a filler 8 of, e.g., polysilicon, and a cap SiO.sub.2 insulating layer 9. Then, polysilicon is deposited on the whole surface by a chemical vapor deposition (CVD) method to form a polysilicon layer, and the layer is patterned by a photolithography technique to form polysilicon layers 11A, 11B and 11C, which become a portion of an SBD electrode, a portion of an electrode for the doped region, and a portion of an interconnection (a wiring), respectively. Thus, the polysilicon layer 11A has a through hole corresponding to the SBD region. The polysilicon layers 11A and 11C are doped with acceptor (p-type) impurities by an ion implantation process, and the polysilicon layer 11B is doped with donor (n-type) impurities by an ion implantation process. The doped impurities are then diffused into the substrate 1 (i.e., the epitaxial silicon layer 4) by a thermal diffusion process to form a P-type guard ring 12 and an N.sup.+ -type region 13 (e.g., a collector region), respectively. An insulating material (e.g., SiO.sub.2) is deposited on the whole surface by a CVD process, to form an insulating layer 14, and the layer 14 is patterned by a photolithography technique to form openings for contact regions. Al (or Al alloy) is then deposited on the whole surface by a sputtering process (or a vapor deposition process) and so as to come into contact with an exposed surface of the substrate 4 in the region of the SBD through the window in the polysilicon layer 11A, and the polysilicon layers 11A, 11B and 11C. Thus, a Schottky barrier diode is formed at the interface between the Al and the silicon indicated as "SBD" in FIG. 1. The deposited Al layer is patterned by a photolithography technique to form Al wirings (i.e., a conductor line 15A including an electrode of the SBD and interconnecting the SBD and the doped region, and another conductor line 15B). Thereafter, another insulating material (e.g., SiO.sub.2) is deposited on the whole surface to form a passivation insulating layer 16, and the layer 16 is selectively etched to form a contact hole, and then a metal (Al or Al alloy) or a combination of a barrier thin metal (TIN, TiW or the like) and Al (or Al alloy) is deposited on the whole surface and is patterned by a photolithography technique to form a predetermined metal wiring (conductor line) 17, whereby a semiconductor device with the SBD is obtained.
Where the SBD is formed by using Al (or Al alloy), the properties of the SBD depend upon the orientation (&lt;100&gt; or &lt;111&gt;) of the silicon single crystalline substrate (wafer). The use of a (100) oriented silicon substrate makes the SBD area layer greater than that in a (111) oriented silicon substrate, and the SBD level does not match a demanded level of a device property, and thus the (111) oriented silicon substrate is widely used.
For miniaturization of the semiconductor device, there is a need to reduce the area (dimensions) of the SBD, and as it is preferable to use a silicon substrate (wafer) having less crystal defects, preferably the (100) oriented silicon substrate is adopted.
Furthermore, the use of the Al wiring (the conductor lines 15A and 15B) requires a photomask alignment step and an etching step in the photolithography technique, with the result that it is necessary to take into account an alignment deviation and an etching shift, which prevent the required miniaturization.